1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to phase change memory devices and related programming methods.
A claim of priority is made to Korean Patent Application No. 10-2006-0094155 filed on Sep. 27, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values, which are used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance, and the crystalline phase exhibits a relatively low resistance.
Phase change memory devices typically use the amorphous state to represent a logical “1” and the crystalline state to represent a logical “0”. The crystalline state is generally referred to as a “set state”, and the amorphous state is referred to as a “reset state”. Accordingly, phase change memory cells in the phase change memory devices typically store a logical “0” by “setting” a phase change material in the memory cells to the crystalline state, and the phase change memory cells stores a logical “1” by “resetting” the phase change material to the amorphous state. Various phase change memory devices are disclosed, for example, U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase change material in a phase change memory device is typically converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material. The phase change material is typically converted to the crystalline state by heating the material at another predetermined temperature below the melting temperature for a period of time. Accordingly, data is written to memory cells in a phase change memory device by converting the phase change material in memory cells of the phase change memory device between the amorphous and crystalline states using heating and cooling as described.
The phase change material in a phase change memory device typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), i.e., a “GST” compound. The GST compound is well suited for a phase change memory device because it can quickly transition between the amorphous and crystalline states by heating and cooling.
At least one type of phase change memory cell comprises a top electrode, a chalcogenide layer, a bottom electrode contact, a bottom electrode, and an access transistor or a diode, wherein the chalcogenide layer is the phase change material of the phase change memory cell. Accordingly, a read operation is performed on the phase change memory cell by measuring the resistance of the chalcogenide layer, and a program operation is performed on the phase change memory cell by heating and cooling the chalcogenide layer as described above. A phase change memory cell typically further comprises a switching element used to control a supply of current to the phase change material for program operations.
In general, the resistance of the phase change material in different phase change memory cells tends to vary due to minor differences in process conditions, programming and reading conditions, and a variety of other factors. As a result, the “set state” and the “reset state” for phase change memory cells are typically characterized by resistance distributions such as the bell shaped curves illustrated in figure (FIG.) 1. In other words, phase change memory cells in the “set state” or the “reset state” can exhibit a wide range of different resistance values.
FIG. 1 is a graph illustrating resistance distributions for phase change memory cells in the “set state” and the “reset state”, respectively. In FIG. 1, resistance “R” of the GST compound in the phase change memory cells is measured along the x-axis, and a number of phase change memory cells in a phase change memory device having each particular resistance value is measured along the y-axis.
In FIG. 1, a first distribution labeled “S1” represents phase change memory cells in the “set state” and a second distribution labeled “R1” represents phase change memory cells in the “reset state”. A sensing margin “SM” exists in FIG. 1 between a maximum value of the first distribution and a minimum value of the second distribution. Also in FIG. 1, a distance between a pair of relatively longer dotted lines represents a desired sensing margin between the first and second distributions.
Because the sensing margin in FIG. 1 is significantly smaller than the desired sensing margin, there is an undesirably high likelihood that phase change memory cells having the distributions illustrated in FIG. 1 will experience read or program errors due to minor variations in read and programming conditions. For example, due to the relatively small sensing margin illustrated in FIG. 1, minor variations in a reference read resistance or slight perturbations in measured resistance values of selected memory cells can result in erroneous readings of the states of the selected memory cells.